Maxim-integrated MAXQ Family Users Guide: MAXQ2000 Supplement Instrukcja Użytkownika Pobierz pdf (Strona 24)

MAXQ Family User’s Guide:

MAXQ2000 Supplement

MAXQ2000 System Clock Modes

Bit 0: (CKCN.0) Clock Divide 0 (CD0); Bit 1: (CKCN.1) Clock Divide 1 (CD1); Bit 2: (CKCN.2) Power Management Mode Enable

(PMME). These three bits control the divide ratio or enable power management mode for the system clock as shown in the MAXQ2000

System Clock Modes table. CD0 and CD1 can always be read, and they can be written as long as PMME = 0.

Setting the PMME bit to 1 activates either the divide-by-256 power management mode or the 32kHz power management mode,

depending on the settings of CD1 and CD0. When PMME is set to 1, CD0 and CD1 cannot be changed; their values will determine the

clock divide ratio that is used when the processor exits power management mode. When the 32kHz power management mode is

active, the high-frequency oscillator amplifier is disabled unless Switchback is enabled.

RGMD SWB PMME

CD1

CD0 SYSTEM CLOCK HIGH-FREQUENCY OSCILLATOR SWITCHBACK

0 0 0 0 0 HFOsc / 1 Running N/A

0 0 0 0 1 HFOsc / 2 Running N/A

0 0 0 1 0 HFOsc / 4 Running N/A

0 0 0 1 1 HFOsc / 8 Running N/A

0 0 1 0 0 HFOsc / 256 Running Not Active

0 1 1 0 0 HFOsc / 256 Running Active

1 0 0 0 0 Ring / 1 Off or Warming Up N/A

1 0 0 0 1 Ring / 2 Off or Warming Up N/A

1 0 0 1 0 Ring / 4 Off or Warming Up N/A

1 0 0 1 1 Ring / 8 Off or Warming Up N/A

1 0 1 0 0 Ring / 256 Off or Warming Up N/A

x 0 1 1 1 32kHz Off Not Active

x 1 1 1 1 32kHz Running Active

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Maxim-integrated MAXQ Family Users Guide: MAXQ2000 Supplement Instrukcja Użytkownika Strona 24