
Table 6. System Register Reset Values
MAXQ Family User’s Guide:
MAXQ2000 Supplement
BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10 BIT 9 BIT 8 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1
AP 00000000
APC 00000000
PSF 10000000
IC 00000000
IMR 00000000
SC 000000s 0
IIR 00000000
CKCN 0 ss00000
WDCN ss000ss0
A[0..15]
0000000000000000
PFX 0000000000000000
IP 1000000000000000
SP 0000000000001111
IV 0000000000000000
LC[0] 0000000000000000
LC[1] 0000000000000000
Offs 00000000
DPC0000000000011100
GR 0000000000000000
GRL 00000000
BP 0000000000000000
GRS0000000000000000
GRH 00000000
GRXL 0000000000000000
FP 0000000000000000
DP[0] 0000000000000000
DP[1] 0000000000000000
Note: Bits marked as “s” have special behavior upon reset; see register descriptions for details.
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