Maxim-integrated MAXQ7666 Instrukcja Użytkownika Pobierz pdf (Strona 257)

MAXQ7665/MAXQ7666 User’s Guide

7-22

7.4 Type 2 Timer/Counter Capture Application Examples

The following examples are used to demonstrate some of the Type 2 timer capture functions. All examples assume that pulse and/or

period measurements do not exceed 2

(i.e., 65,536) input clocks and that capture register holds the desired result.

7.4.1 Measure Low-Pulse Duration

To measure the duration of the first full low pulse seen on the T0 input pin, the Type 2 timer is configured for a single-shot capture, gat-

ing enabled for logic-high, and capture on the rising edge. The CPRL2 bit can optionally be set to generate a reload on the same ris-

ing edge as the capture, if the preconfigured T2R0 value is expected to be needed next.

; ------------------ Reset State: T2R0 = T2V0 = T2C0 = 0000h ------------------------

MOVE T2CFG0, #00000010b ;

; T2DIV[2:0] =000 (/1)

; T2MD =0 (16-bit)

; CCF[1:0] =01 (rising edge)

; C/T2 =0 (timer/capture)

MOVE T2CNA0, #10100111b ; ET2 =1 (enable Timer ints)

; T2OE0 =0 (input)

; T2POL0 =1 (gating level = ‘1’)

; TR2L:TR2 =00 (don’t start timer)

; CPRL2 =1 (reload on capture edge)

; SS2 =1 (single shot mode)

; G2EN =1 (gating enabled)

; ------------------ TCC2 Interrupt : DURATION = T2C0

T0 PIN

CODE EXECUTION:

POINT A

CODE EXECUTION:

POINT B

EVENTS:

1A: GATING CONDITION REMOVED; SINGLE-SHOT CAPTURE CYCLE BEGINS.

2A: RISING EDGE CAUSES CAPTURE/RELOAD; SINGLE-SHOT CAPTURE CYCLE ENDS; DURATION = T2C0.

1B: RISING EDGE CAUSES CAPTURE/RELOAD; SINGLE-SHOT CAPTURE CYCLE BEGINS, TIMER CLOCK GATED SINCE T0 PIN = 1.

2B: GATING CONDITION REMOVED; TIMER RUNS.

3B: RISING EDGE CAUSES CAPTURE/RELOAD; SINGLE-SHOT CAPTURE CYCLE ENDS; DURATION = T2C0.

Figure 7-6. Type 2 Timer Application Example—Measure Low Pulse Width

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