Maxim-integrated MAXQ7666 Instrukcja Użytkownika Strona 1

Functional DiagramsPin Configurations appear at end of data sheet.Functional Diagrams continued at end of data sheet.UCSP is a trademark of Maxim Inte

Memory access from the MAXQ7665/MAXQ7666 is based on a Harvard architecture with separate address spaces for program anddata memory. The simple instru

Bits 2 to 0: ADC Source Select Bits 2 to 0 (ADCS2 to ADCS0). These bits select the ADC conversion start source used to triggeranalog-to-digital conver

3.2.3 DAC Control Register (DCNT)Register Description: DAC Control RegisterRegister Name: DCNTRegister Address: Module 05h, Index 03hBits 15 to 7, 3 t

3.2.4 DAC Input Data Register (DACI)Register Description: DAC Input Data RegisterRegister Name: DACIRegister Address: Module 05h, Index 04hBits 15 to

3.2.6 ADC Data Register (ADCD)Register Description: ADC Data RegisterRegister Name: ADCDRegister Address: Module 05h, Index 08hBits 15 to 12: Reserved

3.2.8 Analog Interrupt Enable Register (AIE)Register Description: Analog Interrupt Enable RegisterRegister Name: AIERegister Address: Module 05h, Inde

3.2.9 Analog Status Register (ASR)Register Description: Analog Status RegisterRegister Name: ASRRegister Address: Module 05h, Index 0BhBit 15: I/O Vol

3.2.10 Oscillator Control Register (OSCC)Register Description: Oscillator Control RegisterRegister Name: OSCCRegister Address: Module 05h, Index 0ChBi

3.3 Analog-to-Digital Converter (ADC) PortThe MAXQ7665/MAXQ7666 contain a low-power, high-precision, 12-bit, 500ksps successive approximation analog-t

MAXQ7665/MAXQ7666 User’s Guide3-183.3.1 ADC SignalsThe MAXQ7665/MAXQ7666 ADC uses 18 external signals (other than analog supply and ground) as explain

MAXQ7665/MAXQ7666 User’s Guide3-19Figure 3-3. Multiplexer Input Connection SchemeAIN14AIN12AIN10AIN8AIN6AIN4AIN2AIN0AIN15AIN13AIN11AIN9AIN7AIN5AIN3AIN

1.2.2 Register SpaceThe MAXQ7665/MAXQ7666 architecture provides a total of 16 register modules. Each of these modules contains 32 registers. Of thesep

MAXQ7665/MAXQ7666 User’s Guide3-203.3.3 True-Differential Analog Input T/HThe equivalent input circuit of Figure 3-4 A and B shows the MAXQ7665/MAXQ76

MAXQ7665/MAXQ7666 User’s Guide3-213.3.4 Unipolar/BipolarThe MAXQ7665/MAXQ7666 ADC produces a digital output that corresponds to the differential analo

MAXQ7665/MAXQ7666 User’s Guide3-223.3.5 Transfer FunctionThe MAXQ7665/MAXQ7666 ADC output is straight binary in unipolar mode. Figure 3-5 shows the MA

MAXQ7665/MAXQ7666 User’s Guide3-23Table 3-5 shows the input range for various PGA settings (PGG2:PGG0) in unipolar mode. When the PGA is used (gain &g

MAXQ7665/MAXQ7666 User’s Guide3-24Table 3-6. Bipolar Code Table (PGA Gain = 1)Table 3-7 shows the input range for various PGA settings (PGG2:PGG0) in

MAXQ7665/MAXQ7666 User’s Guide3-253.3.6 Programmable Gain AmplifierThe MAXQ7665/MAXQ7666 programmable gain amplifier (PGA) receives its inputs from th

MAXQ7665/MAXQ7666 User’s Guide3-263.3.7 Analog Input ProtectionInternal ESD protection diodes limit all analog inputs to AVDD and AGND, allowing the i

MAXQ7665/MAXQ7666 User’s Guide3-273.3.8 ADC ClockThe MAXQ7665/MAXQ7666 ADC clock frequency is controlled by the ADCCD2:ADCCD0 bits in the OSCC control

MAXQ7665/MAXQ7666 User’s Guide3-283.3.10 ADC Conversion Start Sources and TimingThe MAXQ7665/MAXQ7666 ADC supports three different conversion start so

MAXQ7665/MAXQ7666 User’s Guide3-29ADC DUAL-MODE (ADCDUL)ADC CONVERSION SOURCE (ADCS2:ADCS0) ADC CONVERSION TRIGGER ADC CONVERSION DESCRIPTION 000 (Tim

The MAXQ7665/MAXQ7666 peripheral register space (modules 0 to 5) contains registers that access the following peripherals:• General-purpose, 8-bit, I/

MAXQ7665/MAXQ7666 User’s Guide3-30ADC DUAL-MODE (ADCDUL)ADC CONVERSION SOURCE (ADCS2:ADCS0) ADC CONVERSION TRIGGER ADC CONVERSION DESCRIPTION 000 (Tim

MAXQ7665/MAXQ7666 User’s Guide3-31Figure 3-10 shows single-edge-controlled ADC conversion timing when the ADC is in auto shutdown state and the PGA is

MAXQ7665/MAXQ7666 User’s Guide3-32In dual-edged conversions, it is up to the user to provide the required power-up and acquisition delay as explained

MAXQ7665/MAXQ7666 User’s Guide3-333.3.12 Using the ADCThe flow chart in Figure 3-13 highlights all the steps required for initializing and using the A

MAXQ7665/MAXQ7666 User’s Guide3-343.4 Temperature SensorThe MAXQ7665/MAXQ7666 support an internal temperature sensor for local die temperature measure

MAXQ7665/MAXQ7666 User’s Guide3-353.4.1 Temperature Sensor SignalsThe MAXQ7665/MAXQ7666 temperature sensor uses four (one external diode can be connec

MAXQ7665/MAXQ7666 User’s Guide3-36Figure 3-15 shows the nominal transfer function for temperature conversions. Output coding is two’s complement with

MAXQ7665/MAXQ7666 User’s Guide3-373.4.4.1 Differential Temperature MeasurementFor differential temperature measurements, connect the anode of a diode-

MAXQ7665/MAXQ7666 User’s Guide3-38Figure 3-16 shows a simplified functional block diagram of the MAXQ7665/MAXQ7666 DAC.3.5.1 DAC SignalsThe MAXQ7665/M

MAXQ7665/MAXQ7666 User’s Guide3-39Table 3-13 illustrates the relationship between the straight binary input and the analog output voltage.Table 3-13.

1.2.3 Memory OrganizationBeyond the internal register space, memory on the MAXQ7665/MAXQ7666 microcontrollers is organized according to a Harvard arch

MAXQ7665/MAXQ7666 User’s Guide3-403.5.4 DAC Power-DownThe DAC is disabled and fully powered down if the DACE bit in the APE register is cleared. Full

MAXQ7665/MAXQ7666 User’s Guide4-1This section contains the following information:4.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3.1.1.8 Interframe Spacing (Intermission) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4-484.3.1.2 Remote Frame . . . . . . . . .

MAXQ7665/MAXQ7666 User’s Guide4-3Figure 4-1. MAXQ7665/MAXQ7666 CAN 0 Controller Block Diagram . . . . . . . . . . . . . . . . . . . . .4-5Figure 4-2.

MAXQ7665/MAXQ7666 User’s Guide4-4SECTION 4: CONTROLLER AREA NETWORK (CAN) MODULEThe MAXQ7665/MAXQ7666 smart data-acquisition microcontrollers incorpor

MAXQ7665/MAXQ7666 User’s Guide4-5The priority order associated with the CAN module transmitting or receiving a message is determined by the inverse of

MAXQ7665/MAXQ7666 User’s Guide4-64.2 CAN Controller Registers4.2.1 Dual Port Memory Space RegistersThis section summarizes CAN 0 control/status/mask i

MAXQ7665/MAXQ7666 User’s Guide4-74.2.1.1 Dual Port Memory Space Registers for CAN 0CAN 0 CONTROL/STATUS/MASK REGISTERSREGISTER 76543210DUAL PORT ADDRE

MAXQ7665/MAXQ7666 User’s Guide4-8CAN 0 MESSAGE CENTERS 2–14REGISTER 76543210DUAL PORT ADDRESSMessage Center 2 Registers (Similar to Message Center 1)

MAXQ7665/MAXQ7666 User’s Guide4-94.2.2 Control/Status/Mask Register DescriptionsThe CAN control/status/mask registers are located at either the higher

Table 1-3. MAXQ7665A–MAXQ7665D Flash Memory FeaturesMAXQ7665/MAXQ7666 User’s Guide1-12FEATURE MAXQ7665A MAXQ7665B MAXQ7665C MAXQ7665D Flash Type Type

MAXQ7665/MAXQ7666 User’s Guide4-10CAN 0 Media Arbitration Register 0 (C0MA0)CAN 0 Media Arbitration Register 1 (C0MA1)CAN 0 Media Arbitration Register

MAXQ7665/MAXQ7666 User’s Guide4-11CAN 0 Bus Timing Register 0 (C0BT0)Bits 7 and 6: CAN Synchronization Jump Width Select (SJW1 and SJW0). These bits s

MAXQ7665/MAXQ7666 User’s Guide4-12CAN 0 Bus Timing Register 1 (C0BT1)Bit 7: CAN Sampling Rate (SMP). The SMP bit determines the number of samples to b

MAXQ7665/MAXQ7666 User’s Guide4-13CAN 0 Standard Global Mask Register 0 (C0SGM0)CAN 0 Standard Global Mask Register 1 (C0SGM1)CAN Standard Global Mask

MAXQ7665/MAXQ7666 User’s Guide4-14CAN 0 Extended Global Mask Register 1 (C0EGM1)CAN 0 Extended Global Mask Register 2 (C0EGM2)CAN 0 Extended Global Ma

MAXQ7665/MAXQ7666 User’s Guide4-15CAN 0 Message Center 15 Mask Register 0 (C0M15M0)CAN 0 Message Center 15 Mask Register 1 (C0M15M1)CAN 0 Message Cent

MAXQ7665/MAXQ7666 User’s Guide4-16CAN 0 Message Center 15 Mask Register 3 (C0M15M3)CAN Message Center 15 Mask Registers 0 to 3 (C0M15M0 to C0M15M3). T

MAXQ7665/MAXQ7666 User’s Guide4-174.2.3 CAN Message Center Register DescriptionsThe CAN message center registers are located at either the higher orde

MAXQ7665/MAXQ7666 User’s Guide4-18CAN 0 Message Center y Arbitration Register 3 (C0MyAR3)CAN 0 Message Center y Arbitration Registers 0 to 3 (C0MyAR0

MAXQ7665/MAXQ7666 User’s Guide4-19Special Notes for Message Center 15: The ROW bit in message center 15 is associated with an overwrite of the shadow

MAXQ7665/MAXQ7666 User’s Guide1-13Table 1-5. MAXQ7666 Data Flash FeaturesFEATURE MAXQ7666 Flash Type Type F Data Flash Size 256B (128 x 16) 128 Page

MAXQ7665/MAXQ7666 User’s Guide4-20CAN 0 Message Center y Data Byte 0 (C0MyD0)CAN 0 Message Center y Data Byte 1 (C0MyD1)CAN 0 Message Center y Data By

MAXQ7665/MAXQ7666 User’s Guide4-21CAN 0 Message Center y Data Byte 4 (C0MyD4)CAN 0 Message Center y Data Byte 5 (C0MyD5)CAN 0 Message Center y Data By

MAXQ7665/MAXQ7666 User’s Guide4-224.2.4 CAN Global Control and Status Register DescriptionsAll the global CAN controls and status, as well as the indi

MAXQ7665/MAXQ7666 User’s Guide4-23Bit 4: Low-Power Siesta Mode (SIESTA). Setting the SIESTA bit to 1 places the CAN 0 controller into a low-power stat

MAXQ7665/MAXQ7666 User’s Guide4-24processor has removed itself from the BUSOFF condition, it also clears BSS = 0, sets SWINT = 1, and clears both the

MAXQ7665/MAXQ7666 User’s Guide4-254.2.4.2 CAN 0 Status Register (C0S)Register Description: CAN 0 Status RegisterRegister Name: C0SRegister Address: Mo

MAXQ7665/MAXQ7666 User’s Guide4-26C0C.1 = 1, EC96/128 = EC128. In this mode, when EC96/128 = 1 the interrupt flag indicates that either the CAN 0 tran

MAXQ7665/MAXQ7666 User’s Guide4-27Bits 2, 1, 0: CAN 0 Bus Error Status 2, 1, 0 (ER2, ER1, ER0). The ER2:ER0 bits indicate the first type of error that

MAXQ7665/MAXQ7666 User’s Guide4-284.2.4.3 CAN 0 Interrupt Register (C0IR)Register Description: CAN 0 Interrupt RegisterRegister Name: C0IRRegister Add

MAXQ7665/MAXQ7666 User’s Guide4-29The INTIN vector value does not change when a new interrupt source becomes active and the previous one has not yet b

1.2.3.2 Utility ROMA utility ROM (4k x 16) is placed in the upper 32kWord program memory space starting at address 8000h. This utility ROM providesthe

MAXQ7665/MAXQ7666 User’s Guide4-30To properly reflect the value of each interrupt source in the C0IR register, each source must be enabled via the res

MAXQ7665/MAXQ7666 User’s Guide4-312. ERI = 1 and/or ETI = 1 Only (STIE = 0: Hardwired Method) with No Prior Interrupt Active4.2.4.4 CAN 0 Transmit-Err

MAXQ7665/MAXQ7666 User’s Guide4-324.2.4.5 CAN 0 Receive-Error Register (C0RE)Register Description: CAN 0 Receive-Error RegisterRegister Name: C0RERegi

MAXQ7665/MAXQ7666 User’s Guide4-33Bit 6: Increment/Decrement Select (INCDEC). This bit determines the C0DP’s auto-increment/decrement function when AI

MAXQ7665/MAXQ7666 User’s Guide4-344.2.4.8 CAN 0 Data Buffer Register (C0DB)Register Description: CAN 0 Data Buffer RegisterRegister Name: C0DBRegister

MAXQ7665/MAXQ7666 User’s Guide4-354.2.4.9 CAN 0 Receive Message Stored Register (C0RMS)Register Description: CAN 0 Receive Message Stored RegisterRegi

MAXQ7665/MAXQ7666 User’s Guide4-364.2.4.10 CAN 0 Transmit Message Acknowledgement Register (C0TMA)Register Description: CAN 0 Transmit Message Acknowl

MAXQ7665/MAXQ7666 User’s Guide4-374.2.4.11 CAN 0 Message Center 1 to 15 Control Registers (C0M1C to C0M15C)Register Description: CAN 0 Message Center

MAXQ7665/MAXQ7666 User’s Guide4-38Bit 3: External Transmit Request (EXTRQ). (Read/clear only.) When EXTRQ is cleared to 0, there are no pending reques

MAXQ7665/MAXQ7666 User’s Guide4-39Bit 0: Data Updated (DTUP). (Unrestricted read.) When T/R = 0, DTUP can only be cleared to 0 when written by the mic

1.2.3.4 Stack MemoryThe MAXQ7665/MAXQ7666 provide a 16 x 16 hardware stack to support subroutine calls and system interrupts. A 16-bit wide on-chipsta

MAXQ7665/MAXQ7666 User’s Guide4-40Note: The CAN 0 message center 2 to 15 control register bits are identical to those found in the CAN 0 message cente

MAXQ7665/MAXQ7666 User’s Guide4-41Register Description: CAN 0 Message Center 4 Control RegisterRegister Name: C0M4CRegister Address: Module 04h, Index

MAXQ7665/MAXQ7666 User’s Guide4-42Register Description: CAN 0 Message Center 6 Control RegisterRegister Name: C0M6CRegister Address: Module 04h, Index

MAXQ7665/MAXQ7666 User’s Guide4-43Register Description: CAN 0 Message Center 8 Control RegisterRegister Name: C0M8CRegister Address: Module 04h, Index

MAXQ7665/MAXQ7666 User’s Guide4-44Register Description: CAN 0 Message Center 10 Control RegisterRegister Name: C0M10CRegister Address: Module 04h, Ind

MAXQ7665/MAXQ7666 User’s Guide4-45Register Description: CAN 0 Message Center 12 Control RegisterRegister Name: C0M12CRegister Address: Module 04h, Ind

MAXQ7665/MAXQ7666 User’s Guide4-46Register Description: CAN 0 Message Center 14 Control RegisterRegister Name: C0M14CRegister Address: Module 04h, Ind

MAXQ7665/MAXQ7666 User’s Guide4-474.3 CAN OperationsThe CAN2.0B protocol specifies two different message formats: the standard 11-bit (CAN2.0A) and th

MAXQ7665/MAXQ7666 User’s Guide4-484.3.1.1.3 Control Field(Standard and extended format.) The control field is composed of six bits in two fields. The

MAXQ7665/MAXQ7666 User’s Guide4-49Figure 4-6. CRC FieldCRC FIELDCRC SEQUENCECRCDELIMITERACK FIELDDATA FIELD ORCONTROL FIELDFigure 4-7. Acknowledge Fie

1.2.3.6 Pseudo-Von Neumann Memory AccessThe pseudo-Von Neumann memory mapping is straightforward if there is no memory overlapping among the program,

MAXQ7665/MAXQ7666 User’s Guide4-504.3.1.2 Remote Frame(Standard and extended format.) The remote frame is transmitted by a CAN controller to request t

MAXQ7665/MAXQ7666 User’s Guide4-514.3.1.3 Error FrameThe error frame is transmitted by a CAN controller when the CAN processor detects a bus error. Th

MAXQ7665/MAXQ7666 User’s Guide4-524.4 General CAN Protocol-Related Issues4.4.1 Bit StuffingThe CAN processor performs a function termed bit stuffing i

MAXQ7665/MAXQ7666 User’s Guide4-534.6 Initializing the CAN ControllerSoftware initialization of the CAN controller begins with the setting of the soft

MAXQ7665/MAXQ7666 User’s Guide4-54Figure 4-12. CAN Interrupt LogicUPDATE CAN 0INTERRUPTREGISTERCAN 0/1 STATUS REGISTERCAN 0STATUSREGISTERREADCAN 0 CON

MAXQ7665/MAXQ7666 User’s Guide4-554.8 Arbitration/Masking ConsiderationsThe CAN processor is designed to evaluate and determine if an incoming message

MAXQ7665/MAXQ7666 User’s Guide4-564.9 Transmitting and Receiving MessagesAll CAN data is sent and received through message centers. All CAN message ce

MAXQ7665/MAXQ7666 User’s Guide4-574.9.4 Receiving/Responding to Remote Frame RequestsThe remote frame request is handled like a data frame with data l

MAXQ7665/MAXQ7666 User’s Guide4-58Case 2: Software-Initiated Reply(Using TIH as gating control.) CAN module wants to receive an RFR and wait for softw

MAXQ7665/MAXQ7666 User’s Guide4-59Case 4: Software-Initiated Reply(Reply through different message center, using TIH as gating control.) CAN controlle

• The utility ROM can be accessed as data with offset at 8000h.• One page (byte access mode) or two pages (word access mode) can be accessed as data w

MAXQ7665/MAXQ7666 User’s Guide4-60Important Information Concerning ID Changes When Awaiting Data from a Previous Remote Frame RequestThe use of accept

MAXQ7665/MAXQ7666 User’s Guide4-61Case 2: WTOE = 0 (Overwrites Disabled)1) Software configures message centers 1 and 2 with the same arbitration value

MAXQ7665/MAXQ7666 User’s Guide4-62The autobaud feature for the CAN module is enabled by setting the autobaud bit (C0C.2). Setting this bit activates a

MAXQ7665/MAXQ7666 User’s Guide4-634.14 BUSON/BUSOFF Recovery and Error Counter OperationThe CAN module contains two peripheral registers that allow so

MAXQ7665/MAXQ7666 User’s Guide4-644.15 Bit TimingBit timing in the CAN2.0B specification is based on a unit called the nominal bit time. The nominal b

MAXQ7665/MAXQ7666 User’s Guide4-65The CAN 0 bus timing register 0 (C0BT0) contains the control bits for the PHASE_SEG1 and PHASE_SEG2 time segments as

MAXQ7665/MAXQ7666 User’s Guide4-66The following restrictions apply to the above equations: The nominal bit time applies when a synchronization edge fa

MAXQ7665/MAXQ7666 User’s Guide4-674.16 CAN Bus ActivityThe CAN bus activity (CAN0BA) status is active when a CAN bus activity is detected on the CAN i

MAXQ7665/MAXQ7666 User’s Guide5-1This section contains the following information:5.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . .

MAXQ7665/MAXQ7666 User’s Guide5-2Figure 5-1. Oscillator/Clock Generation Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .5-4F

For the modulo increment or decrement operation, the selected range of bits in AP are incremented or decremented. However, if thesebits roll over or u

MAXQ7665/MAXQ7666 User’s Guide1-18Figure 1-5. CDA Functions (Word Access Mode)PHYSICAL DATA0000h8000h0100hDATA MEMORY015CDA1 = 0CDA1 = 1MAXQ7665/MAXQ7

MAXQ7665/MAXQ7666 User’s Guide5-3SECTION 5: OSCILLATOR/CLOCK GENERATION MODULEThe MAXQ7665/MAXQ7666 oscillator/clock generation module supplies the sy

5-4MAXQ7665/MAXQ7666 User’s GuideFigure 5-1. Oscillator/Clock Generation Module Block DiagramPOWER-ON RESETDVDDRESETXIN/HF-CLKXOUTSTOPHFIC(1:0)HIGH-FR

5-5MAXQ7665/MAXQ7666 User’s Guide5.2 Oscillator/Clock Generation RegistersThe MAXQ7665/MAXQ7666 oscillator/clock generation module registers are descr

5.2.2 Oscillator Control Register (OSCC)The OSCC register contains the oscillator enable and configuration bits.Register Description: Oscillator Contr

Bits 9 and 8: High-Frequency Crystal Input Capacitance Select 1 and 0 (HFIC1 and HFIC0). These bits select the input capaci-tance of the on-chip high-

5.2.3 System Clock Control Register (CKCN)The 8-bit CKCN register is part of the system register group and used to support system clock generation. It

MAXQ7665/MAXQ7666 User’s Guide5-9• The SPI module’s SS (slave select input) signal is asserted in slave mode.• A CAN bus activity on its data input (C

MAXQ7665/MAXQ7666 User’s Guide5-105.2.4 Watchdog Timer Control Register (WDCN)The 8-bit WDCN register is part of the system register group and used to

Bit 2: Watchdog Reset Flag (WTRF). This flag is set to 1 when the watchdog resets the processor. Software can check this bit fol-lowing a reset to det

MAXQ7665/MAXQ7666 User’s Guide5-125.3 System Clock GenerationAll functional modules in the MAXQ7665/MAXQ7666 are synchronized to a single system clock

MAXQ7665/MAXQ7666 User’s Guide1-19Figure 1-6. CDA Functions (Byte Access Mode)UTILITY ROMPHYSICAL DATA0000h8000hA000h9000hFFFFhA100h0000h8000h0200hFFF

Figure 5-2. Oscillator Startup FlowYESYESPOWER-ON RESETSTART UP 7.6MHzINTERNAL RC OSCILLATOR8.6ms POWER-UP COUNTER DELAYRESET 16-BITPOWER-UP COUNTERIN

MAXQ7665/MAXQ7666 User’s Guide5-14The crystal oscillator/resonator is disabled upon power-up, as the default mode for the MAXQ7665/MAXQ7666 is to run

MAXQ7665/MAXQ7666 User’s Guide5-15ENABLE HF OSCILLATORHFE = 1SELECT CLOCK DIVIDE VALUE:PMME, CD1 AND CD0 BITSCRYSTAL/RESONATOR-BASEDCODE EXECUTIONSELE

MAXQ7665/MAXQ7666 User’s Guide5-165.3.3 External Clock (Direct Input)The MAXQ7665/MAXQ7666 can also obtain the system clock signal directly from an ex

5.3.5 External Crystal-Fail Detection and Automatic SwitchoverThe MAXQ7665/MAXQ7666 have a high-frequency oscillator-fail detection circuit. An automa

MAXQ7665/MAXQ7666 User’s Guide5-185.4 Watchdog TimerThe watchdog timer is a user-programmable clock counter that can serve as a time-base generator, a

Table 5-4. Interrupt and Reset Functions for WatchdogTable 5-5. Watchdog Timeout SelectionsThe watchdog timeout selection is made using bits WD1 (WDCN

MAXQ7665/MAXQ7666 User’s Guide5-205.5 Power Management ModeThere are two major sources of power dissipation in CMOS circuitry. The first is static dis

5.5.2 Switchback ModeWhen power management mode is active, the MAXQ7665/MAXQ7666 operate at a reduced clock rate. Although execution continuesas norma

MAXQ7665/MAXQ7666 User’s Guide6-1This section contains the following information:6.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.3.9 Program and Data Memory Mapping Example 1: MAXQ7665BFigures 1-7, 1-8, and 1-9 show the mapping of physical memory segments into the program an

MAXQ7665/MAXQ7666 User’s Guide6-2Figure 6-1. UART Synchronous Mode (Mode 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 6: SERIAL I/O MODULEThe MAXQ7665/MAXQ7666 serial I/O module provides access to a universal asynchronous receiver/transmitter (UART) for serial

MAXQ7665/MAXQ7666 User’s Guide6-4Figure 6-1. UART Synchronous Mode (Mode 0)DIVIDEBY 12D7D6D5D4D3D2D1D0LOADCLOCKOUTPUT SHIFT REGISTERS0LATCHRECEIVE DAT

6.1.1 UART PinsThe MAXQ7665/MAXQ7666 UART supports dedicated transmit and receive pins as described in Table 6-2.Table 6-2. MAXQ7665/MAXQ7666 UART Pin

MAXQ7665/MAXQ7666 User’s Guide6-6Serial Mode DefinitionBit 6: Serial Port Mode Bit 1 (SM1). See theSerial Mode Definitiontable.Bit 5: Serial Port Mode

6.2.2 Serial Port 0 Mode Register (SMD0)Register Description: Serial Port 0 Mode RegisterRegister Name: SMD0Register Address: Module 00h, Index 1EhBit

6.2.3 Phase Register 0 Register (PR0)Register Description: Phase Register 0Register Name: PR0Register Address: Module 00h, Index 1FhBits 15 to 0: Phas

6.3 Modes of OperationA detailed description of the MAXQ7665/MAXQ7666 UART modes is given in this section.6.3.1 UART Mode 0This mode is used to commun

MAXQ7665/MAXQ7666 User’s Guide6-10Figure 6-3. UART Mode 0DIVIDEBY 12D7D6D5D4D3D2D1D0LOADCLOCKOUTPUT SHIFT REGISTERS0LATCHRECEIVE DATA BUFFER WRSBUF0RD

MAXQ7665/MAXQ7666 User’s Guide6-11Figure 6-4. UART Mode 1DIVIDEBY 4D7D6D5D4D3D2D1D001LOADCLOCKTRANSMIT SHIFT REGISTERS0LATCHRECEIVE DATA BUFFER WRSBUF

MAXQ7665/MAXQ7666 User’s Guide1-2132k x 16PROGRAM FLASHPROGRAMSPACEEXECUTING FROMDATA SPACE(BYTE MODE)DATA SPACE(WORD MODE)0000h7FFFh4k x 16UTILITY RO

MAXQ7665/MAXQ7666 User’s Guide6-126.3.3 UART Mode 2This mode uses a total of 11 bits in asynchronous, full-duplex communication as illustrated in Figu

MAXQ7665/MAXQ7666 User’s Guide6-13Figure 6-5. UART Mode 2DIVIDEBY 2D7D6D5D4D3D2D1D001LOADCLOCKTRANSMIT SHIFT REGISTERS0LATCHRECEIVE DATA BUFFER WRSBUF

MAXQ7665/MAXQ7666 User’s Guide6-14Figure 6-6. UART Mode 3D0 D1 D2 D3 D4 D5 D6 D7 RB8 STOPD0 D1 D2 D3 D4 D5 D6 D7 TB8 STOPRECEIVE TIMINGTRANSMIT TIMING

MAXQ7665/MAXQ7666 User’s Guide6-156.4 Baud-Rate GenerationEach mode of operation has a baud-rate generation technique associated with it. The baud-rat

MAXQ7665/MAXQ7666 User’s Guide6-166.4.4 Baud-Clock GeneratorThe baud-clock generator is basically a phase accumulator that produces a baud clock as th

MAXQ7665/MAXQ7666 User’s Guide6-176.5 Framing Error DetectionA framing error occurs when a valid stop bit is not detected. This results in the possibl

MAXQ7665/MAXQ7666 User’s Guide7-1SECTION 7: TYPE 2 TIMER/COUNTER MODULEThis section contains the following information:7.1 Architecture . . . . . . .

MAXQ7665/MAXQ7666 User’s Guide7-27.4 Type 2 Timer/Counter Capture Application Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7-

MAXQ7665/MAXQ7666 User’s Guide7-3SECTION 7: TYPE 2 TIMER/COUNTER MODULEThe MAXQ7665/MAXQ7666 microcontrollers have three Type 2 timer/counter modules.

MAXQ7665/MAXQ7666 User’s Guide7-4T2Vx REGISTER16-BIT UP COUNTERT2Rx REGISTER16-BIT RELOADCAPTUREEQUALOVERFLOWRELOADCLOCKT2Cx REGISTER16-BIT CAPTURE/CO

1.2.3.10 Program and Data Memory Mapping Example 2: MAXQ7666Figures 1-10, 1-11, and 1-12 show the mapping of physical memory segments into the program

MAXQ7665/MAXQ7666 User’s Guide7-5T2CLx REGISTER(LOWER BYTE OF T2Cx)8-BIT CAPTURE/COMPARE LOWT2Lx REGISTER(LOWER BYTE OF T2Vx)8-BIT UP COUNTER LOWT2RLx

7.1.1 Type 2 Timer/Counter I/O PinsEach Type 2 timer/counter module normally supports one primary input/output pin that is referred to as Tx. Table 7-

MAXQ7665/MAXQ7666 User’s Guide7-77.2.1 Type 2 Status/Control RegistersThe MAXQ7665/MAXQ7666 timer/counter module registers T2CFGx (configuration), T2C

MAXQ7665/MAXQ7666 User’s Guide7-8Bits 2 and 1: Capture/Compare Function Select Bits (CCF1 and CCF0). These bits, in conjunction with the C/T2 bit, sel

MAXQ7665/MAXQ7666 User’s Guide7-9Bit 6: Type 2 Timer Output Enable 0 (T2OE0). This register bit enables the timer output function for the external Tx

MAXQ7665/MAXQ7666 User’s Guide7-10Bit 0: Gating Enable (G2EN). This bit enables the external Tx pin to gate the input clock to the 16-bit (T2MD = 0) o

MAXQ7665/MAXQ7666 User’s Guide7-117.2.2 Type 2 Timer Value RegistersThe MAXQ7665/MAXQ7666 timer/counter registers T2Vx (timer value) and T2Hx (timer v

7.2.2.2 Type 2 Timer/Counter Value High Register (T2Hx)Register Description: Type 2 Timer/Counter Value High RegisterRegister Name: T2Hx (x = 0, 1, 2)

MAXQ7665/MAXQ7666 User’s Guide7-137.2.3 Type 2 Reload RegistersThe MAXQ7665/MAXQ7666 timer/counter module registers T2Rx (timer reload) and T2RHx (tim

7.2.3.2 Type 2 Timer/Counter Reload High Register (T2RHx)Register Description: Type 2 Timer/Counter Reload High RegisterRegister Name: T2RHx (x = 0, 1

MAXQ7665/MAXQ7666 User’s Guide1-23PROGRAMSPACEDATA SPACE(BYTE MODE)DATA SPACE(WORD MODE)8k x 16PROGRAM FLASH0000h1FFFh16k x 8PROGRAM FLASH(CDA0 = 0)00

MAXQ7665/MAXQ7666 User’s Guide7-157.2.4 Type 2 Capture/Compare RegistersThe MAXQ7665/MAXQ7666 timer/counter module registers T2Cx (timer capture/compa

7.2.4.2 Type 2 Timer/Counter Capture/Compare High Register (T2CHx)Register Description: Type 2 Timer/Counter Capture/Compare High RegisterRegister Nam

MAXQ7665/MAXQ7666 User’s Guide7-177.3 Type 2 Timer/Counter Operation ModesThe MAXQ7665/MAXQ7666 Type 2 timer/counter supports six operation modes. Tab

MAXQ7665/MAXQ7666 User’s Guide7-18T2CLxEDGE DETECTIONAND GATINGC/T2TR2LT2MDT2CLKCCF[1:0]G2ENTR2SS2T2POL[0]T2LxT2Lx COMPARE MATCHT2Vx COMPARE MATCHOR T

MAXQ7665/MAXQ7666 User’s Guide7-197.3.1 16-Bit Timer: Auto-Reload/CompareThe 16-bit auto-reload/compare mode for the Type 2 timer is in effect when th

MAXQ7665/MAXQ7666 User’s Guide7-207.3.2 16-Bit Timer: Capture ModeThe 16-bit capture mode requires that some event trigger the capture. Normally, this

MAXQ7665/MAXQ7666 User’s Guide7-21T2DIV[2:0]SYSTEM CLOCKT2CLKDIVIDE-BY-NPRESCALEFigure 7-5. Type 2 Timer Clock7.3.4 Dual 8-Bit TimersThe dual 8-bit ti

MAXQ7665/MAXQ7666 User’s Guide7-227.4 Type 2 Timer/Counter Capture Application ExamplesThe following examples are used to demonstrate some of the Type

MAXQ7665/MAXQ7666 User’s Guide7-237.4.2 Measure High-Pulse Duration RepeatedlyTo measure the duration of high pulses seen on the T0 input pin repeated

MAXQ7665/MAXQ7666 User’s Guide7-247.4.3 Measure Period To measure the period of the signal seen on the T0 input pin, the Type 2 timer is configured fo

1.2.4.2 Interrupt System OperationThe interrupt handler hardware responds to any interrupt event when it is enabled. An interrupt event occurs when an

MAXQ7665/MAXQ7666 User’s Guide7-257.4.4 Measure Duty Cycle RepeatedlyTo measure the duty cycle of the signal seen on the T0 input pin, the Type 2 time

MAXQ7665/MAXQ7666 User’s Guide7-267.4.5 Overflow/Interrupt on Cumulative TimeTo cause an overflow only when the T0 pin has been low for some cumulativ

7.5 Type 2 Timer/Counter Compare Application ExampleThe following example is used to demonstrate the Type 2 timer compare function.7.5.1 A Simple Wave

MAXQ7665/MAXQ7666 User’s Guide8-1This section contains the following information:8.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 8: GENERAL-PURPOSE I/O MODULE The MAXQ7665/MAXQ7666 smart data-acquisition microcontrollers provide 8 port pins for general-purpose I/O, which

8.1.1 Port PinsThe MAXQ7665/MAXQ7666 port P0 pins are summarized in Table 8-1.8.2 Port RegistersThe following peripheral registers control the general

8.2.2 External Interrupt Flag Register (Port 0) (EIF0)Register Description: External Interrupt Flag Register (Port 0)Register Name: EIF0Register Addre

Bit 2: Bit 2 Edge Detect (IE2). This bit is set when a negative edge (IT2 = 1) or a positive edge (IT2 = 0) is detected on the interrupt2 pin. Setting

8.2.4 External Interrupt Enable Register (Port 0) (EIE0)Register Description: External Interrupt Enable Register (Port 0)Register Name: EIE0Register A

8.2.5 Port 0 Direction Register (PD0)Register Description: Port 0 Direction RegisterRegister Name: PD0Register Address: Module 00h, Index 10hBits 15 t

MAXQ7665/MAXQ7666 User’s Guide1-25SYSTEM MODULESWDIF(WATCHDOG)EWDI(LOCAL ENABLE)MODULE 1IM1(MODULE 1 ENABLE)MODULE 0IE0ESI(LOCAL ENABLES)EX0-EX7IE1IE7

8.2.6 External Interrupt Edge Select Register (Port 0) (EIES0)Register Description: External Interrupt Edge Select Register (Port 0)Register Name: EIE

8.3 GPIO OperationFrom a software perspective, the MAXQ7665/MAXQ7666 port P0 appears as a group of peripheral registers with unique addresses andis ad

Table 8-3. Port Pin Special and Alternate FunctionsMAXQ7665/MAXQ7666 User’s Guide8-10PORT PINFUNCTIONTYPEFUNCTION ENABLED WHEN MULTIPLEXING/PRIORITIZA

8.3.4 Port Pin Examples8.3.4.1 Port Pin Example 1: Driving Outputs on Port 0move PO0, #000h ; Set all outputs lowmove PD0, #0FFh ; Set all P0 pins to

MAXQ7665/MAXQ7666 User’s Guide9-1This section contains the following information:9.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . .

MAXQ7665/MAXQ7666 User’s Guide9-2Figure 9-1. SPI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 9: SERIAL PERIPHERAL INTERFACE (SPI) MODULEThe MAXQ7665/MAXQ7666 serial peripheral interface (SPI) module provides an independent serial commu

MAXQ7665/MAXQ7666 User’s Guide9-49.1.1 SPI PinsThe SPI signals are shown in Table 9-1.Table 9-1. MAXQ7665/MAXQ7666 SPI Pins9.2 SPI Peripheral Register

9.2.2 SPI Control Register (SPICN)Register Description: SPI Control RegisterRegister Name: SPICNRegister Address: Module 01h, Index 07hBits 15 to 8: R

MAXQ7665/MAXQ7666 User’s Guide9-6Bit 3: Mode-Fault Flag (MODF). This bit is the mode-fault flag for SPI master mode operation. When mode fault detecti

1.2.4.4 Interrupt Prioritization by SoftwareAll interrupt sources of the MAXQ7665/MAXQ7666 microcontrollers naturally have the same priority. However,

9.2.3 SPI Configuration Register (SPICF)Register Description: SPI Configuration RegisterRegister Name: SPICFRegister Address: Module 01h, Index 08hBit

MAXQ7665/MAXQ7666 User’s Guide9-89.2.4 SPI Clock Register (SPICK)Register Description: SPI Clock RegisterRegister Name: SPICKRegister Address: Module

9.3 SPI OperationThe MAXQ7665/MAXQ7666 SPI can be viewed as a synchronous serial I/O port that shifts a data stream of 8 or 16 bits between periph-era

MAXQ7665/MAXQ7666 User’s Guide9-109.3.2 SPI Slave OperationThe MAXQ7665/MAXQ7666 SPI module operates in slave mode when the MSTM bit is cleared to log

9.3.3 SPI Transfer FormatsDuring an SPI transfer, data is simultaneously transmitted and received over two serial data lines with respect to a single

MAXQ7665/MAXQ7666 User’s Guide9-129.3.4 SPI Character LengthsTo flexibly accommodate different SPI transfer data lengths, the character length for any

9.5.2 Receive OverrunSince the receive direction of the MAXQ7665/MAXQ7666 SPI is double buffered, there is no overrun condition as long as the receive

This section contains the following information:10.1 TAP Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MAXQ7665/MAXQ7666 User’s Guide10-2Figure 10-1. MAXQ7665/MAXQ7666 TAP and TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . .10-3Figur

SECTION 10: TEST ACCESS PORT (TAP)10.1 TAP OverviewThe MAXQ7665/MAXQ7666 incorporate a test access port (TAP) and TAP controller for communication wit

MAXQ7665/MAXQ7666 User’s Guide1-27INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAGWatchdog Interrupt IMS (IMR.7) EWDI (WDCN.6) WDIF (WDC

MAXQ7665/MAXQ7666 User’s Guide10-410.2.1 TAP PinsThe TAP is formed by four interface signals as described in Table 10-1. The TAP signals are multiplex

10.3 TAP Interface ControlOnce an application has been loaded and starts running, the MAXQ7665/MAXQ7666 JTAG TAP interface can be controlled by the TA

MAXQ7665/MAXQ7666 User’s Guide10-610.4 TAP Controller OperationThe MAXQ7665/MAXQ7666 TAP controller is formed by a finite state machine that provides

MAXQ7665/MAXQ7666 User’s Guide10-710.4.2 Run-Test-IdleAs illustrated in Figure 10-2, the run-test-idle state is an intermediate state for getting to o

10.4.4 DR-Scan SequenceOnce the instruction register has been configured to a desired state (mode), transactions are performed via a data buffer regis

MAXQ7665/MAXQ7666 User’s Guide10-9Figure 10-3. TAP Controller Debug Mode—IR-Scan ExampleNEW INSTRUCTIONINSTRUCTION REGISTERTCKTMSTDITDOCONTROLSTATEIR

MAXQ7665/MAXQ7666 User’s Guide10-10Figure 10-4. TAP Controller Debug Mode—DR-Scan ExampleOLD DATANEW DATADATA REGISTERTCKTMSTDITDOCONTROLSTATESHIFTREG

MAXQ7665/MAXQ7666 User’s Guide__________________________________________________________________________________11-1SECTION 11: IN-CIRCUIT DEBUG MODET

MAXQ7665/MAXQ7666 User’s Guide11-2Figure 11-1. In-Circuit Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 11: IN-CIRCUIT DEBUG MODEThe MAXQ7665/MAXQ7666 are equipped with embedded debug hardware and embedded ROM firmware developed for the purposeof

MAXQ7665/MAXQ7666 User’s Guide1-1SECTION 1: MAXQ7665/MAXQ7666 CORE ARCHITECTUREThis section contains the following information:1.1 Overview . . . . .

MAXQ7665/MAXQ7666 User’s Guide1-28INTERRUPT MODULE ENABLE BIT LOCAL ENABLE BIT INTERRUPT FLAGCAN 0 Message Center 3 Receive IM4 (IMR.4) ERI (C0M3C.5

The debug engine is supported by five functional registers:• ICDB: The ICDB register is an 8-bit data register that supports exchanging command/data b

11.2.2 In-Circuit Debug Temporary 1 Register (ICDT1)The ICDT1 register is read/write accessible by the CPU only in background mode or debug mode. This

Bit 5: Break-On Register Enable (REGE). The REGE bit is used to enable the break-on register function. When the REGE bit is set to1, BP4 and BP5 are u

11.2.4 In-Circuit Debug Flag Register (ICDF)Register Description: In-Circuit Debug Flag RegisterRegister Name: ICDFRegister Address: Module 02h, Index

11.2.6 In-Circuit Debug Address Register (ICDA)The debug engine uses the ICDA register to store addresses so that ROM code may view that information.

11.2.8 System Control Register (SC)Register Description: System Control RegisterRegister Name: SCRegister Address: Module 08h, Index 08hBit 7: Test Ac

11.3 Debug Engine OperationTo enable a communication link between the host and the MAXQ7665/MAXQ7666 debug engine, the debug instruction (010b) mustbe

Table 11-1 shows the background mode commands supported by the MAXQ7665/MAXQ7666. Encodings not listed in this table arenot supported in background mo

11.3.2 Breakpoint RegistersThe MAXQ7665/MAXQ7666 incorporate six host-configurable breakpoint registers (BP0–BP5) for establishing different types of

11.3.2.2 Breakpoint Register 4 (BP4)Register Description: Breakpoint Register 4Register Name: BP4This register is accessible only via background mode

1.3 ProgrammingThe following section provides a programming overview of the MAXQ7665/MAXQ7666. For full details on the instruction set, as well asSyst

11.3.2.3 Breakpoint Register 5 (BP5)This register is accessible only through background mode read/write commands.When (REGE = 0): This register serves

11.3.4 Debug ModeThere are two ways to enter debug mode from background mode: 1) issuance of the debug command directly by the host through theTAP com

Internally, the ROM can ascertain when new data is available or when it can output the next data byte via the TXC flag. The TXC flagis an important in

11.3.6 Read-Register Map Command Host-ROM InstructionA read-register map command reads out data contents for all implemented system and peripheral reg

11.3.9 Debug Mode Special ConsiderationsThe following are special considerations when using debug mode.The debug engine cannot be operated reliably wh

11.3.10.3 Data Memory Write CommandWhen invoking this command, ICDA should be set to the word address of the location to write to, and ICDD should be

MAXQ7665/MAXQ7666 User’s Guide12-1SECTION 12: IN-SYSTEM PROGRAMMINGThis section contains the following information:12.1 Bootstrap-Loader Mode . . . .

SECTION 12: IN-SYSTEM PROGRAMMINGThe MAXQ7665/MAXQ7666 are equipped with a bootstrap loader as part of the utility ROM firmware. The main function of

12.2 In-System Programming Peripheral RegistersThe MAXQ7665/MAXQ7666 in-system programming peripheral registers are described here. All the in-system

12.2.2 System Control Register (SC)Register Description: System Control RegisterRegister Name: SCRegister Address: Module 08h, Index 08hBit 7: Test Ac

Generally, prefixing operations can be inserted automatically by the assembler as needed, so that (for example)move DP[0], #1234hactually assembles a

12.3 JTAG Bootloader OperationThe MAXQ7665/MAXQ7666 JTAG bootloader uses the same status bit handshaking hardware as is used for in-circuit debugging.

12.4.1 Entering a PasswordA password can be entered via the TAP interface directly by issuing the unlock-password debug-mode command. The unlock-passw

All commands in Family 0 can be executed without first matching the password. All other commands (in Families 1x through Fx) arepassword protected; th

Command 05h—Get Supported CommandsThe SupportL (LSB) and SupportH (MSB) bytes form a 16-bit value that indicates which command families this bootloade

Command 09h—Get Utility ROM VersionCommand 0Ah—Set Word/Byte Mode AccessThe Mode byte should be 0 to set byte access mode or 1 to set word access mode

12.5.3 Family 2 Commands: Dump Variable Length (Password Protected)Command 20h—Dump Code Variable LengthThis command has a slightly different format d

12.5.5 Family 4 Commands: Verify Variable Length (Password Protected)Command 40h—Verify Code Variable LengthThis command operates in the same manner a

12.5.8 Family 9 Commands: Load Fixed Length (Password Protected)Command 90h—Load Code Fixed LengthThis command loads a block of 128 bytes into the pro

MAXQ7665/MAXQ7666 User’s Guide13-1SECTION 13: HARDWARE MULTIPLIER MODULEThis section contains the following information:13.1 Hardware Multiplier Organ

MAXQ7665/MAXQ7666 User’s Guide13-2SECTION 13: HARDWARE MULTIPLIER MODULEThe MAXQ7665/MAXQ7666 microcontrollers include a hardware multiplier module to

1.3.3.4.1 8-Bit Destination ← Low Byte (16-Bit Source)The simplest transfer possibility would be loading an 8-bit register with the low byte of a 16-b

13.2 Hardware Multiplier Peripheral Registers13.2.1 Hardware Multiplier Control Register (MCNT)Register Description: Hardware Multiplier Control Regis

Bit 3: Operand Count Select (OPCS). This bit defines how many operands must be loaded to trigger a multiply or multiply-accumu-late/subtract operation

13.2.3 Multiplier Operand B Register (MB)Register Description: Multiplier Operand B RegisterRegister Name: MBRegister Address: Module 001, Index 02hBi

13.2.5 Multiplier Accumulator 1 Register (MC1)Register Description: Multiplier Accumulator 1 RegisterRegister Name: MC1Register Address: Module 001, I

13.2.7 Multiplier Read Register 1 (MC1R)Register Description: Multiplier Read Register 1Register Name: MC1RRegister Address: Module 001, Index 0ChBits

13.3 Hardware Multiplier ControlsThe selection of operation to be performed by the multiplier is determined by four control bits in the MCNT register:

13.8 Accessing the MultiplierThere are no restrictions on how quickly data is entered into the operand registers or on the order of data entry. The on

13.9 MAXQ7665/MAXQ7666 Hardware Multiplier ExamplesThe following are code examples of multiplier operations.;Unsigned Multiply 16-bit x 16-bitmove MC

MAXQ7665/MAXQ7666 User’s Guide14-1SECTION 14: MAXQ7665/MAXQ7666 INSTRUCTION SET SUMMARYThis section contains the following information:ADD/ADDC src .

MAXQ7665/MAXQ7666 User’s Guide14-2RETI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

If the high byte needs to be cleared to 00h, the operation can be shortened by transferring only the GRL byte to the 16-bit destination(example follow

MAXQ7665/MAXQ7666 User’s Guide14-3SECTION 14: MAXQ7665/MAXQ7666 INSTRUCTION SET SUMMARYMNEMONIC DESCRIPTION 16-BIT INSTRUCTION WORD STATUS BITS AFFECT

MAXQ7665/MAXQ7666 User’s Guide14-4MNEMONIC DESCRIPTION 16-BIT INSTRUCTION WORD STATUS BITS AFFECTED AP INC/DEC NOTES {L/S}JUMP src IP  IP + src or

MAXQ7665/MAXQ7666 User’s Guide14-5ADD/ADDC srcAdd/Add with CarryDescription: The ADD instruction sums the active accumulator (Acc or A[AP]) and the sp

MAXQ7665/MAXQ7666 User’s Guide14-6AND srcLogical ANDDescription: Performs a logical-AND between the active accumulator (Acc) and the specified src dat

MAXQ7665/MAXQ7666 User’s Guide14-7{L/S}CALLsrc{Long/Short} Call to SubroutineDescription: Performs a call to the subroutine destination specified by s

MAXQ7665/MAXQ7666 User’s Guide14-8CMPsrcCompare AccumulatorDescription: Compare for equality between the active accumulator and the least significant

MAXQ7665/MAXQ7666 User’s Guide14-9CPL C Complement Carry FlagDescription: Logically complements the Carry (C) Flag.Status Flags: COperation: C ← ~CEnc

MAXQ7665/MAXQ7666 User’s Guide14-10{L/S}JUMPsrcUnconditional {Long/Short} JumpDescription: Performs an unconditional jump as determined by the src spe

MAXQ7665/MAXQ7666 User’s Guide14-11{L/S}JUMP C/{L/S}JUMP NC, srcConditional {Long/Short} Jump on Status FlagL/S}JUMP Z/{L/S}JUMP NZ, src{{L/S}JUMP E/{

MAXQ7665/MAXQ7666 User’s Guide14-12JUMP NZ Z=0: IP ← IP + src (relative) -or- src (absolute)Operation: Z=1: IP ← IP + 1Encoding: 15 0Example(s): JUMP

• XOR src (Logical XOR active accumulator with source)• CPL (Bit-wise complement active accumulator)• NEG (Negate active accumulator)• SLA (Arithmetic

MAXQ7665/MAXQ7666 User’s Guide14-13MOVE dst, srcMove DataDescription: Moves data from a specified source (src) to a specified destination (dst). A lis

MAXQ7665/MAXQ7666 User’s Guide14-14MOVE dst, srcMove DataTable 14-3. Destination Specifier CodesData Transfer dst (16-bit) ← src (16-bit): dst[15:0]

MAXQ7665/MAXQ7666 User’s Guide14-15Example(s): MOVE A[0], A[3] ; A[0] ← A[3]MOVE DP[0], #110h ; DP[0] ← #0110h (PFX[0] register used); MOVE PFX[0],

MAXQ7665/MAXQ7666 User’s Guide14-16MOVE C, Acc.<b> Move Accumulator Bit to Carry FlagDescription: Replaces the Carry (C) status flag with the sp

MAXQ7665/MAXQ7666 User’s Guide14-17MOVE C, #1 Set Carry FlagDescription: Sets the Carry (C) processor status flag.Status Flag: C ← 1Operation: C ← 1En

MAXQ7665/MAXQ7666 User’s Guide14-18NEG Negate AccumulatorDescription: Performs a negation (2's complement) of the active accumulator and returns

MAXQ7665/MAXQ7666 User’s Guide14-19OR Acc.<b>Logical OR Carry Flag with Accumulator BitDescription: Performs a logical-OR between the Carry (C)

MAXQ7665/MAXQ7666 User’s Guide14-20POPI dst Pop Word from the Stack Enable InterruptsDescription: Pops a single word from the stack (@SP) to the speci

MAXQ7665/MAXQ7666 User’s Guide14-21RET Return from SubroutineDescription: RET pops a single word from the stack (@SP) into the Instruction Pointer (IP

MAXQ7665/MAXQ7666 User’s Guide14-22RET NCOperation: C=0: IP ← @SP--C=1: IP ← IP +1Encoding: 15 0Example(s): RET NC ; C=1, return (RET) does not occurR

For the modulo increment or decrement operation, the selected range of bits in AP are incremented or decremented. However, if thesebits roll over or u

MAXQ7665/MAXQ7666 User’s Guide14-23RETI Return from InterruptDescription: RETI pops a single word from the stack (@SP) into the Instruction Pointer (I

MAXQ7665/MAXQ7666 User’s Guide14-24RETI ZOperation: Z=1: IP ← @SP--INS ← 0Z=0: IP ← IP + 1Encoding: 15 0Example(s): RETI Z ; Z=0, return from interrup

MAXQ7665/MAXQ7666 User’s Guide14-25RL/RLC Rotate Left AccumulatorCarry Flag (Ex/In)clusiveDescription: Rotates the active accumulator left by a single

MAXQ7665/MAXQ7666 User’s Guide14-26RR/RRC Rotate Right AccumulatorCarry Flag (Ex/In)clusiveDescription: Rotates the active accumulator right by a sing

MAXQ7665/MAXQ7666 User’s Guide14-27SLA/SLA2/SLA4 Shift Accumulator Left ArithmeticallyOne, Two, or Four TimesDescription: Shifts the active accumulato

MAXQ7665/MAXQ7666 User’s Guide14-28SR/SRA/SRA2/SRA4 Shift Accumulator Right/Shift Accumulator Right ArithmeticallyOne, Two, or Four TimesDescription:

MAXQ7665/MAXQ7666 User’s Guide14-29SRA2 Operation: 15 Active Accumulator (Acc) 0 Carry FlagAcc.[13:0] ← Acc.[15:2]Acc.[15:14] ← Acc.

MAXQ7665/MAXQ7666 User’s Guide14-30SUB/SUBB srcSubtract /Subtract with BorrowDescription: Subtracts the specified src from the active accumulator (Acc

MAXQ7665/MAXQ7666 User’s Guide14-31XCH Exchange Accumulator BytesDescription: Exchanges the upper and lower bytes of the active accumulator.Status Fla

MAXQ7665/MAXQ7666 User’s Guide14-32XOR src Logical XORDescription: Performs a logical-XOR between the active accumulator (Acc or A[AP]) and the specif

1.3.5.4 ALU Operations Using Only the Active AccumulatorThe following arithmetic and logical operations operate only on the active accumulator.cpl ; A

SECTION 15: UTILITY ROM (SPECIFIC TOMAXQ7665A–MAXQ7665D WITH TYPE A FLASH)MAXQ7665/MAXQ7666 User’s Guide15-1This section contains the following inform

MAXQ7665/MAXQ7666 User’s Guide15-2SECTION 15: UTILITY ROM (SPECIFIC TO MAXQ7665A–MAXQ7665DWITH TYPE A FLASH)The MAXQ7665 utility ROM includes routines

15.1 In-Application Programming FunctionsFunction: flashEraseSectorSummary: Erases (programs to FFFFh) a sector of flash memory.Inputs: A[0]: Word add

Function: moveDP0incSummary: Reads the byte/word value pointed to by DP[0], then increments DP[0].Inputs: DP[0]: Address to read from.Outputs: GR: Dat

Function: moveDP1decSummary: Reads the byte/word value pointed to by DP[1], then decrements DP[1].Inputs: DP[1]: Address to read from.Outputs: GR: Dat

MAXQ7665/MAXQ7666 User’s Guide15-6Function: copyBufferSummary: Copies LC[0] bytes/words from DP[0] to BP[OFFS].Inputs: DP[0]: Address to copy from.BP[

MAXQ7665/MAXQ7666 User’s Guide15-715.4 ROM Example 1: Calling A MAXQ7665 Utility ROM Function DirectlyThis example shows the direct addressing method

MAXQ7665/MAXQ7666 User’s Guide15-815.5 ROM Example 2: Calling A MAXQ7665 Utility ROM Function IndirectlyThe second example shows the indirect addressi

SECTION 16: UTILITY ROM (SPECIFIC TO MAXQ7666 WITH TYPE F FLASH)MAXQ7665/MAXQ7666 User’s Guide16-1This section contains the following information:16.1

MAXQ7665/MAXQ7666 User’s Guide16-2SECTION 16: UTILITY ROM (SPECIFIC TO MAXQ7666 WITH TYPE FFLASH)The MAXQ7666 utility ROM includes routines that provi

1.3.6.2 Zero FlagThe Zero flag (PSF.7) is a dynamic flag that reflects the current state of the active accumulator Acc. If all bits in the active accu

16.1 In-Application Programming FunctionsFunction: programFlashWritePageSummary: Writes an entire 32-word/64-byte program flash page.Inputs: DP[0]: Wo

Function: programFlashEraseAllSummary: Erases (programs to FFFFh) all locations in program flash memory.Inputs: None.Outputs: Carry: Set on error and

MAXQ7665/MAXQ7666 User’s Guide16-5Function: dataFlashErasePageSummary: Erases (programs to FFFFh) two pages (1 page = 1 word) of the data flash memory

MAXQ7665/MAXQ7666 User’s Guide16-616.2 Data Transfer FunctionsFunction: moveDP0Summary: Reads the byte/word value pointed to by DP[0].Inputs: DP[0]: A

Function: moveDP1incSummary: Reads the byte/word value pointed to by DP[1], then increments DP[1].Inputs: DP[1]: Address to read from.Outputs: GR: Dat

MAXQ7665/MAXQ7666 User’s Guide16-8Function: moveFPdecSummary: Reads the byte/word value pointed to by BP[OFFS] then decrements OFFS.Inputs: BP[OFFS]:

MAXQ7665/MAXQ7666 User’s GuideREVISION NUMBERREVISION DATEDESCRIPTIONPAGES CHANGED 0 12/07 Initial release. —REVISION HISTORY386Maxim Integrated 160

• MOVE Acc.<b>, C (Set selected active accumulator bit to Carry)• AND Acc.<b> (Carry = Carry AND selected active accumulator bit)• OR Acc.

1.3.3.1 Loading an 8-Bit Register with an Immediate Value . . . . . . . . . . . . . . . . . . . . .1-301.3.3.2 Loading a 16-Bit Register with a 16-Bi

1.3.7.3 Conditional JumpsConditional jumps transfer program execution based on the value of one of the status flags (C, E, Z, S). Except where noted f

If loop execution speed is critical and a relative jump cannot be used, one might consider preloading an internal 16-bit register withthe src loop add

INS is set automatically on entry to the interrupt handler and cleared automatically on exit (RETI).IntHandler:push PSF ; save C since used in identi

The POP instruction removes a value from the stack and then decrements the stack pointer. The @SP-- stack access mnemonic is theassociated source spec

Each data pointer (DP[n]) and Frame Pointer base (BP) register is actually implemented internally as a 17-bit register (e.g., 16:0). The FramePointer

move @BP[--Offs], @BP[Offs++]move @DP[0], @DP[0]++move @DP[1], @DP[1]++move @BP[Offs], @BP[Offs++]move @DP[0], @DP[0]--move @DP[1], @DP[1]--move @BP[O

MAXQ7665/MAXQ7666 User’s Guide1-44REGISTER BITREGISTER1514131211109876543210 — — — — AP.3 AP.2 AP.1 AP.0 AP 08h[00h] 0 0 0 0 0 0 0 0 CLR IDS —

MAXQ7665/MAXQ7666 User’s Guide1-45REGISTER BITREGISTER1514131211109876543210GR.15 GR.14 GR.13 GR.12 GR.11 GR.10 GR.9 GR.8 GR.7 GR.6 GR.5 GR.4 GR.3 GR.

MAXQ7665/MAXQ7666 User’s Guide1-461.4.1 Accumulator Pointer Register (AP)Register Description: Accumulator Pointer RegisterRegister Name: APRegister A

Bits 2 to 0: Accumulator Pointer Auto-Increment/Decrement Modulus (MOD2 to MOD0). If these bits are set to a non-zero value,the accumulator pointer (A

1.3.10 Accessing Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-411.4 System Register Descr

1.4.4 Interrupt and Control Register (IC)Register Description: Interrupt and Control RegisterRegister Name: ICRegister Address: Module 08h, Index 05hB

1.4.6 System Control Register (SC)Register Description: System Control RegisterRegister Name: SCRegister Address: Module 08h, Index 08hBit 7: Test Acc

1.4.7 Interrupt Identification Register (IIR)The first six bits in this register indicate interrupts pending in modules 0 to 5, one bit per module. Th

1.4.9 Watchdog Timer Control Register (WDCN)The 8-bit WDCN register is part of the system register group and used to provide system control. It contro

1.4.11 Prefix Register (PFX[n])Register Description: Prefix RegisterRegister Name: PFX[n]Register Address: Module 0Bh, Index 0nhBits 15 to 0: Prefix R

1.4.12 Instruction Pointer Register (IP)Register Description: Instruction Pointer RegisterRegister Name: IPRegister Address: Module 0Ch, Index 00hBits

1.4.14 Interrupt Vector Register (IV)Register Description: Interrupt Vector RegisterRegister Name: IVRegister Address: Module 0Dh, Index 02hBits 15 to

1.4.16 Loop Counter 1 Register (LC[1])Register Description: Loop Counter 1 RegisterRegister Name: LC[1]Register Address: Module 0Dh, Index 07hBits 15

1.4.18 Data Pointer Control Register (DPC)Register Description: Data Pointer Control RegisterRegister Name: DPCRegister Address: Module 0Eh, Index 04h

1.4.19 General Register (GR)Register Description: General RegisterRegister Name: GRRegister Address: Module 0Eh, Index 05hBits 15 to 0: General Regist

Figure 1-1. MAXQ7665/MAXQ7666 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-5Figure 1-2. MAXQ7665/MAXQ7666 Tr

1.4.21 Frame Pointer Base Register (BP)Register Description: Frame Pointer Base RegisterRegister Name: BPRegister Address: Module 0Eh, Index 07hBits 1

1.4.23 General Register High Byte (GRH)Register Description: General Register High ByteRegister Name: GRHRegister Address: Module 0Eh, Index 09hBits 7

1.4.25 Frame Pointer Register (FP)Register Description: Frame Pointer RegisterRegister Name: FPRegister Address: Module 0Eh, Index 0BhBits 15 to 0: Fr

1.4.27 Data Pointer 1 Register (DP[1])Register Description: Data Pointer 1 RegisterRegister Name: DP[1]Register Address: Module 0Fh, Index 07hBits 15

Note: Names that appear in bold italics indicate that all bits of a register are read-only.Table 1-10. MAXQ7665/MAXQ7666 Peripheral Register MapMAXQ76

MAXQ7665/MAXQ7666 User’s Guide1-63REGISTER BITREGISTER1514131211109876543210— — — — — — — — PO0.7 PO0.6 PO0.5 PO0.4 PO0.3 PO0.2 PO0.1 PO0.0 PO0 00h[00

MAXQ7665/MAXQ7666 User’s Guide1-64REGISTER BITREGISTER15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0— — — — — — — — OF MCW CLD SQU OPCS MSUB MMAC SUS MCNT 01h[

MAXQ7665/MAXQ7666 User’s Guide1-65REGISTER BITREGISTER1514131211109876543210— — — — — — — — ET2 T2OE0 T2POL0 TR2L TR2 CPRL2 SS2 G2EN T2CNA0 02h[00h] 0

MAXQ7665/MAXQ7666 User’s Guide1-66REGISTER BITREGISTER1514131211109876543210— — — — — — — — — T2DIV2 T2DIV1 T2DIV0 T2MD CCF1 CCF0 C/T2 T2CFG1 02h[11h]

MAXQ7665/MAXQ7666 User’s Guide1-67REGISTER BITREGISTER15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0— — — — — — — — ET2 T2OE0 T2POL0 TR2L TR2 CPRL2 SS2 G2EN T2

SECTION 1: MAXQ7665/MAXQ7666 CORE ARCHITECTURE1.1 OverviewThe MAXQ7665/MAXQ7666 are low-power, high-performance, 16-bit RISC microcontrollers based on

MAXQ7665/MAXQ7666 User’s Guide1-68REGISTER BITREGISTER15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0— — — — — — — — ERIE STIE PDE SIESTA CRST AUTOB ERCS SWINT

MAXQ7665/MAXQ7666 User’s Guide1-69REGISTER BITREGISTER15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0— — — — — — — — MSRDY ETI ERI INTRQ EXTRQ MTRQ ROW/TIH DTUP

MAXQ7665/MAXQ7666 User’s Guide1-70REGISTER BITREGISTER15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0— — — — — — — — — — VIOBI1 VIOBI0 VDBI1 VDBI0 VDBR1 VDBR0 V

MAXQ7665/MAXQ7666 User’s Guide2-1SECTION 2: POWER-SUPPLY/SUPERVISORY MONITORING MODULEThis section contains the following information:2.1 Architecture

MAXQ7665/MAXQ7666 User’s Guide2-2Figure 2-1. MAXQ7665/MAXQ7666 Power-Supply Block Diagram . . . . . . . . . . . . . . . . . . . . . . . .2-4Figure 2-

SECTION 2: POWER-SUPPLY/SUPERVISORY MONITORING MODULEThe MAXQ7665/MAXQ7666 power-supply/supervisory monitoring module supports dedicated supply pins t

MAXQ7665/MAXQ7666 User’s Guide2-4Figure 2-1. MAXQ7665/MAXQ7666 Power-Supply Block DiagramAVDDAGNDAGNDDVDDIODVDDIOREGENGNDIOANALOGMODULE(MUX, ADC, PGA,

2.1.1 Power-Supply/Supervisory Module PinsThe power-supply module signals are shown in Table 2-1.Table 2-1. MAXQ7665/MAXQ7666 Power-Supply/Supervisory

MAXQ7665/MAXQ7666 User’s Guide2-62.2 Power-Supply/Supervisory Monitoring RegistersThe MAXQ7665/MAXQ7666 power-supply/supervisory monitoring peripheral

Bits 3, 2: DVDD Brownout Interrupt Threshold Bits 1, 0 (VDBI1, VDBI0). These bits are used to select the brownout interrupt thresh-old level for the D

1.1.2 Instruction SetAs part of the MAXQ family, the MAXQ7665/MAXQ7666 use the standard 16-bit MAXQ20 instruction set, with all instructions a fixed 1

MAXQ7665/MAXQ7666 User’s Guide2-82.2.2 Analog Power Enable Register (APE)The APE register contains the power-enable bits to control and turn on/off th

2.2.3 Analog Interrupt Enable Register (AIE)The AIE register is used to enable interrupts from a variety of analog sources including DVDDIO and DVDD b

MAXQ7665/MAXQ7666 User’s Guide2-102.2.4 Analog Status Register (ASR)The ASR register reports the status of the DVDD and DVDDIO supply brownout detecti

2.3 Supply ConfigurationThe MAXQ7665/MAXQ7666 use three supplies to power the internal analog, digital core, and digital I/O circuits. The supplies ar

MAXQ7665/MAXQ7666 User’s Guide2-122.4 Linear RegulatorThe MAXQ7665/MAXQ7666 contain a +3.3V, low dropout (LDO) linear regulator. The regulator powers

2.5.1 Power-Up CounterAn independent power-up counter functions as the startup counter to count 65,536 cycles of the internal 7.6MHz RC oscillator fro

MAXQ7665/MAXQ7666 User’s Guide2-14Figure 2-5. MAXQ7665/MAXQ7666 Brownout ResetNOMINALDVDD (+3.3V)+3.06V+2.77VDGNDDVDD BROWNOUT RESETTHRESHOLD RANGEVDB

2.5.3 Reset OutputThe MAXQ7665/MAXQ7666 assert the RESET signal during power-up and also during reset conditions caused by an internal source(such as

MAXQ7665/MAXQ7666 User’s Guide2-16Figure 2-7. DVDD Brownout Interrupt Threshold DetectionNOMINALDVDD (+3.3V)BROWNOUTRESET TRIGGERPOINTBROWNOUTINTERRUP

Figure 2-8. DVDDIO Brownout Interrupt Threshold Detection NOMINALDVDDIO (+5.0V)DVDDIOBROWNOUTINTERRUPTDVDDIO BROWNOUTINTERRUPT THRESHOLDRANGE VIOBI[1:

1.2 ArchitectureThe MAXQ7665/MAXQ7666 architecture is designed to be modular and expandable. Top-level instruction decoding is extremely sim-ple and b

2.7.2 External ResetDuring normal operation, the MAXQ7665/MAXQ7666 devices are placed into an external reset mode by holding the RESET pin low forat l

MAXQ7665/MAXQ7666 User’s Guide3-1SECTION 3: ANALOG I/O MODULEThis section contains the following information:3.1 Architecture . . . . . . . . . . . .

3.4 Temperature Sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-343.4.1 Tem

MAXQ7665/MAXQ7666 User’s Guide3-3Figure 3-1. Analog I/O Module Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MAXQ7665/MAXQ7666 User’s Guide3-4Table 3-1. Analog I/O Module Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SECTION 3: ANALOG I/O MODULEThe MAXQ7665/MAXQ7666 contain an ultra-low-power precision analog I/O module for measuring and controlling a host of senso

3.1.1 Analog I/O PinsThe analog I/O module has 24 pins associated with the analog functions on the microcontroller. Table 3-1 shows the external inter

3.2 Analog I/O Module Control and Status RegistersThe analog I/O module uses the following control and status registers.3.2.1 Analog Power Enable Regi

3.2.2 ADC Control Register (ACNT)Register Description: ADC Control RegisterRegister Name: ACNTRegister Address: Module 05h, Index 02hBits 15 to 11: AD

When ADCMX4 is cleared, the ADC input channel is configured for a differential voltage measurement. When ADCMX0 is set, the ADC’spositive and negative