MAXQ Family User’s Guide:
MAXQ8913 Supplement
22-2
22.1.1 I
2
C Data Buffer Register (I2CBUF, M1[06h])
Bits 9:0: This register is used as the read and write data buffer for I
2
C data and address transmissions.
22.1.1.1 I
2
C Data Read and Write
Data for I
2
C transfer is read and written to this location. The I
2
C transmit and receive buffers are internally stored
separately; however, both are accessed through this buffer. For data transfers, only the low eight bits (I2CBUF[7:0])
are significant.
22.1.1.2 I
2
C Address Transmission
When transmitting an I
2
C address, the address should be loaded into I2CBUF[6:0] for a 7-bit address (if I2CEA = 0)
and into I2CBUF[9:0] for a 10-bit address (if I2CEA = 1). Bits 8 and 9 are effectively write-only since there is no cir-
cumstance under which reading them returns useful data.
22.1.2 I
2
C Status Register (I2CST, M3[01h])
Bit 15: I
2
C Bus Busy (I2CBUS). This bit is set to 1 when a START/repeated START condition is detected and cleared
to 0 when the STOP condition is detected. This bit is reset to 0 on all forms of reset and when I2CEN = 0. This bit is
controlled by hardware and is read-only.
Bit 14: I
2
C Busy (I2CBUSY). This bit is used to indicate the current status of the I
2
C module. The I2CBUSY is set to 1
when the I
2
C controller is actively participating in a transaction or when it does not have control of the bus. This bit is
controlled by hardware and is read-only.
Bits 13:12: Reserved. Read returns 0.
Bit 11: I
2
C STOP Interrupt Flag (I2CSPI). This bit is set to 1 when a STOP condition (P) is detected. This bit must be
cleared to 0 by software once set. Setting this bit to 1 by software causes an interrupt if enabled.
Bit 10: I
2
C SCL Status (I2CSCL). This bit reflects the logic state of the SCL signal. This bit is set to 1 when SCL is at
a logic-high (1), and cleared to 0 when SCL is at a logic-low (0). This bit is controlled by hardware and is read-only.
Note: ADCONV cannot be written when PMME = 1 and SWB = 0.
*Can be written only when I2CBUSY = 0.
Bit #
15 14 13 12 11 10 9 8
Name I2CBUS I2CBUSY — — I2CSPI I2CSCL I2CROI I2CGCI
Reset 0 0 0 0 0 0 0 0
Access r r r r rw r rw rw
Bit #
7 6 5 4 3 2 1 0
Name I2CNACKI I2CALI I2CAMI I2CTOI I2CSTRI I2CRXI I2CTXI I2CSRI
Reset 0 0 0 0 0 0 0 0
Access rw rw rw rw rw rw rw rw
Bit #
15 14 13 12 11 10 9 8
Name — — — — — — I2CBUF
Reset 0 0 0 0 0 0 0 0
Access r r r r r r w* w*
Bit #
7 6 5 4 3 2 1 0
Name I2CBUF
Reset 0 0 0 0 0 0 0 0
Access rw* rw* rw* rw* rw* rw* rw* rw*
Maxim Integrated
(158 strony)
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Komentarze do niniejszej Instrukcji