10-3 __________________________________________________________________________________________________________
MAXQ7667 User’s Guide
10.2 Hardware Multiplier Peripheral Registers
10.2.1 Hardware Multiplier Control Register (MCNT)
R
egister Description:
H
ardware Multiplier Control Register
Register Name: MCNT
R
egister Address:
M
odule 01h, Index 00h
Bits 15 to 8: Reserved.
Read returns 0, write ignored.
Bit 7: Overflow Flag (OF). This bit is set to logic 1 when an overflow occurred for the last operation. This bit can be set for accumu-
lation/subtraction operations or unsigned multiply-negate attempts. This bit is automatically cleared to 0 following a reset, starting a
multiplier operation, or setting of the CLD bit to 0.
Bit 6: MC Register Write Select (MCW). The state of the MCW bit determines if an operation result will be placed into the accumula-
tor registers (MC).
0 = The result is written to the MC registers.
1 = The result is not written to the MC registers (MC register content is unchanged).
Bit 5: Clear Data Registers (CLD). This bit initializes the operand registers and the accumulator of the multiplier. When it is set to 1,
the contents of all data registers and the OF bit are cleared to 0 and the operand load counter is reset immediately. This bit is cleared
by har
dwar
e automatically
. W
riting a 0 to this bit has no effect.
Bit 4: Square-Function Enable (SQU). This bit suppor
ts the hardwar
e square function. When this bit is set to logic 1, a square oper-
ation is initiated after an operand is written to either the MA or the MB register. Writing data to either of the operand registers writes to
both registers and triggers the specified square or square-accumulate/subtract operation. Setting this bit to 1 also overrides the OPCS
bit setting. When SQU is cleared to logic 0, the hardware square function is disabled.
0 = Square function disabled.
1 = Square function enabled.
Bit #
15 14 13 12 11 10 98
Name — ———————
R
eset 0 0 0 0 0 0 0 0
A
ccess r r rrrrrr
B
it #
7
6543210
Name OF MCW CLD SQU OPCS MSUB MMAC SUS
Reset 0 0 0 0 0 0 0 0
Access r rw rw rw rw rw rw rw
r = read, w = write
Note: This register is cleared to 0000h on all forms of reset.
(114 strony)
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